1. Field of the Invention
The present invention generally relates to semiconductor devices, and in particular, the present invention relates to a device and method for maintaining a field transistor in an off state notwithstanding long-term exposure of field oxides to radiation.
2. Description of the Related Art
FIG. 1 illustrates a somewhat typical configuration in which two n-channel MOS devices 101 and 102 are positioned side-by-side along the surface of a common bulk substrate 103. The device 101 includes an n-region source 104 and an n-region drain 105 defining a channel region therebetween. Positioned over the channel region of the device 101 are a gate oxide layer 106 and a gate electrode 107. Similarly, the device 102 includes a gate oxide layer 110 and a gate electrode 111 positioned over another channel region defined between an n-region drain 108 and an n-region source 109. The non-gated portion between the devices 101 and 102 is covered by a field-oxide 112. Typically, a number of metal overlays functioning as device interconnects will be positioned atop the field-oxides. Such an interconnect is shown by reference number 113 in FIG. 1.
As is apparent from FIG. 1, the n-regions 105 and 108, the field-oxide 112 and the metal overlay 113 together constitute the necessary parts of a transistor device. As such, if the potential of the overlay 113 exceeds a given potential, the intermediate region between the devices 101 and 102 will be inverted. In other words, a pseudo-channel will exist between the devices 101 and 102. In some operational states, the drain 105 of the device 101 and the drain 108 of the device 102 will be at different potentials. For example, the drain 105 may carry a logic 1 while the drain 108 is carrying a logic 0. In such a state, the presence of a pseudo-channel between the devices would result in substantial leakage.
To avoid this problem, the field-oxides are typically made much thicker than the gate-oxides in the device configuration, thereby increasing the absolute value of the threshold voltage in the field regions relative to that of the gated regions of the device. This prevents inversion of the field-oxide regions at potentials required for normal device operation.
However, notwithstanding the thick field-oxides, long-term exposure to radiation (which, for example, can occur in military and space applications) can reduce the field-oxide thresholds to the point where pseudo-channels are generated. Accumulation of charges in field-oxides can result, for example, from radiation exposure in the form of cosmic rays, solar winds, X-rays, and the like. The charge accumulations induced by such irradiation cause both an increase in the fixed charge within the field-oxide and an increase in the insulator-semiconductor interfacial-trap (or surface) concentration, which in turn can reduce the field region threshold voltage. This problem is especially acute for the relatively thick field-oxides which tend to accumulate more charges. In fact, it has been shown that the shift in threshold voltage for both the fixed charge and the interfacial traps is at least roughly proportional to the oxide thickness. The field-oxide may have a thickness on the order of 5000 .ANG., whereas the gate-oxide is typically around 50 .ANG.. Thus, while the shift in gate voltage resulting from radiation might be only a few tens of millivolts for the gate regions, the impact on the field threshold shift might be one-hundred times greater.
A number of techniques are known for attempting to counter the effects of field threshold shifts induced by radiation. For example, one technique commonly used to offset the field threshold shift is to heavily dope the silicon surface. Analogous to a threshold adjust implant in the gate of a transistor, a field implant can be employed to shift the field threshold. A disadvantage of this approach is the increase in junction capacitance resulting from the heavy implant. Other techniques involve growing the oxide in such a way as to minimize charge trapping sites. That is, special techniques are sometimes employed to "harden" the oxides, i.e., to make the oxides less sensitive to incoming radiation.
Yet another technique which has been used to control field leakage (primarily in the days before the ion implantation approach) is the use of the "field plate". This is a conductive layer or plate placed above the silicon surface that acts like a common gate for all the field transistors. The plate is then held at a fixed potential to offset the field threshold voltage shift, and thus keep the field transistors in an off-state. That fixed potential could be something like -5 volts in the case of n-channel field transistors, and +5 volts in the case of p-channel field transistors. As such, one common plate would be provided for the n-channel field transistors, and a second common plate would be provided for the p-channel field transistors. An advantage of this approach is that it is not necessary to modify the part of the fabrication process involved in active device formation. Rather, the relatively simple addition of one or more conductive layers to form the field plates is all that is needed. On the other hand, one disadvantage of the field-plate approach is that the use of the relatively high fixed potentials results in a certain degree of constant power dissipation. Further, even in the presence of the fixed potentials, long-term exposure to excessive radiation can still create pseudo-channels in the field regions. Thus, the field transistors can be switched to an on-state without warning, making device failure imminent.